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fastmachinelearning/wa-hls4ml-projects

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Citation text from the card

@article{10.1145/3787490,
    author = {Hawks, Benjamin and Weitz, Jason and Demler, Dmitri and Tame-Narvaez, Karla and Plotnikov, Dennis and Rahimifar, Mohammad Mehdi and Rahali, Hamza Ezzaoui and Therrien, Audrey C. and Sproule, Donovan and Khoda, Elham E. and Smith, Keegan A. and Marroquin, Russell and Di Guglielmo, Giuseppe and Tran, Nhan and Duarte, Javier and Loncar, Vladimir},
	title = {wa-hls4ml: A Benchmark and Surrogate Models for hls4ml Resource and Latency Estimation},
	year = {2026},
	issue_date = {June 2026},
	publisher = {Association for Computing Machinery},
	address = {New York, NY, USA},
	volume = {19},
    number = {2},
	issn = {1936-7406},
	url = {https://doi.org/10.1145/3787490},
	doi = {10.1145/3787490},
	abstract = {As machine learning (ML) is increasingly implemented in hardware to address real-time challenges in scientific applications, the development of advanced toolchains has significantly reduced the time required to iterate on various designs. These advancements have solved major obstacles, but also exposed new challenges. For example, processes that were not previously considered bottlenecks, such as hardware synthesis, are becoming limiting factors in the rapid iteration of designs. To mitigate these emerging constraints, multiple efforts have been undertaken to develop an ML-based surrogate model that estimates resource usage of ML accelerator architectures. We introduce wa-hls4ml, a benchmark for ML accelerator resource and latenc

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